ADCs are used in a wide range of electrical and electronic equipment, in fields as diverse as sensing and instrumentation, audio and video devices, and communications equipment.
The performance requirements of ADCs vary according to the application, but in general, it is important that ADCs are both linear, that is to say, the change in digital output is proportional to a change in analog input, and repeatably accurate, that is to say, the ADC output should be the same for the same inputs and provide a proper representation of the input.
For many applications, the speed of the ADC conversion is important. For instance, ADCs used for the conversion of analog video signals into a digital signal may require fast operation: to support a frame rate of 10 s or 100 s of hertz, the ADC may be required to sample and convert the signal at a rate of 10 s or 100 s of MegaHertz.
One convenient and commonly used design of ADC, which is capable of operating at high speeds, is the so-called pipeline design of ADC. In a pipeline ADC, the conversion of the sampled analog signal occurs over several stages. At each stage, a simple conversion of the analog signal is made to extract typically one, or one and a half, “bits” of the digital signal. This digital signal is reconverted into an analog equivalent, and subtracted from the analog input to the stage, resulting in a residue (analog) signal. This residual signal is amplified and passed to the next stage, in which the same operation is carried out. The resulting (second) residue is passed to a third stage, and so on.
Thus, in a pipeline ADC, the analog signal passes along a conceptual “pipeline”, and as it passes along the pipeline, it is sequentially and progressively converted to a digital signal, starting with the most significant bit, and concluding with the least significant bit.
An example architecture of a pipeline ADC is shown schematically in FIG. 1. The first block 1 is a dedicated sample-and-hold (SH) that samples the input signal and buffers it to drive the following stages. Each of the pipeline stages after the front-end SH 1 resolve a number of bits. A pipeline stage, “stage i”, 2, consists of a SH 3 to sample the input from a previous stage. An ADC 4 quantizes the held sample and the digital output obtained is converted back to the analog domain, at a Digital-to-Analog Converter (DAC) 5 and subtracted from the held sample at adder 6. The residue signal obtained after the subtraction point is amplified by amplifier 7 and fed to the next stage. The functionality contained inside the pipeline stages can be implemented with a switched-capacitor circuit. In the last stage 8 (stage k) only the residue of the previous stage needs to be quantized and this functionality is implemented with only an ADC. The bits from the different stages are combined in the digital domain to form the final output word of the pipeline ADC.
As shown in FIG. 1 the stage after the first block also contains a SH. To save power the dedicated SH in the first block can be omitted and its functionality can be taken over by the SH in the first intermediate stage. Doing so makes the design of the first pipeline stage more complicated because of the increased demands.
The basic architecture of a switched-capacitor implementation of a pipeline stage without the need of a dedicated front-end SH is shown in FIG. 2(a). Switches φ1 (which comprises separate switches φ1 and φ1e) and φ2 are alternately high. During the time φ1 (which comprises separate switches φ1 and φ1e in FIG. 2(a)) is high the voltage on capacitor Cs tracks the input and capacitor Cf is discharged. On the falling edge of φ1 the instantaneous voltage on capacitor Cs is sampled and the ADC 21 is strobed to quantize the input.
In a practical implementation the timing of the component switches of φ1, that is to say, switches φ1 and φ1e, is adjusted such that φ1e leads φ1, as shown in FIG. 2(b). FIG. 2(b) shows that both clock signals φ1 and φ1e are non-overlapping high with clock signal φ2 (that is to say, closed). Clock signal φ1e is a slightly advanced version of clock signal φ1. During the time φ1 and φ1e are high the voltage on capacitor Cs tracks the input and capacitor Cf is discharged. It is on the falling edge of φ1e (which is ahead of φ1) that the instantaneous voltage on capacitor Cs is sampled and the ADC 21 is strobed to quantize the input. The advanced clock φ1e ensures that the critical sample moment is determined by switch φ1e. This is commonly referred to as bottom-plate sampling.
The DAC 22 outputs an analog signal representing the quantized result of the ADC. During the time that φ2 is high the operational amplifier 23 (“opamp”) maintains virtual ground at the negative input, assuming it has sufficient open-loop gain, and capacitor Cs is charged to the DAC output voltage. Thereby an amount of charge is transferred to capacitor Cf. This amount of charge QΔ is equal to Qq−Qs, where the charge Qq is CsVDAC and charge Qs is CsVin(ts). The residue output voltage then becomes (equation 1):V=−QΔ/Cf=Cs/Cf.(Vin(ts)−VDAC)
The next period, when φ1 and φ1e are high again, capacitor Cs is connected to the input again to track the input and take a new sample on the falling edge of φ1e. 
The signal on capacitor Cs at the start of the track period is correlated to a previous input sample which introduces inter-symbol interference (ISI). This ISI can cause distortion when the settling is non linear or the signal on Cs has a non-linear correlation with the previous sample. For the pipeline stage shown in FIG. 2 the signal on Cs is a quantized representation of the previous sample at the start of the track period. Since quantizing a signal is a non-linear operation this pipeline stage introduces distortion regardless whether the settling toward a new sample is linear.
One problem which is associated with switched-capacitor pipeline stages without dedicated SH is that the charge on the sample capacitor at the beginning of the track period, and the voltage corresponding to this charge, is correlated to a previous input sample. This results in ISI. This ISI can cause distortion when the settling is non linear or the signal on the sample capacitor has a non-linear correlation with the previous sample.
It is known from P. Bognor et al. “A 14b 100 MS/s Digitally Self-Calibrated Pipelined ADC in 0.13 m CMOS”. In ISSCC Digest of Technical Papers, 2006, to compensate the charge on the sample capacitor by an opposite charge sampled on a dummy capacitor. The opposite charges cancel each other and ISI, which would otherwise result in distortion, is avoided in this way. This idea is also disclosed in US patent application US2004-0239378A1. The sample and hold phases are carried out immediately after each other, and a separate reset phase before the sample phase is not necessitated. However, one disadvantage of this arrangement is that the capacitive load of the input driver and reference buffers is doubled thereby resulting in an increase in the device's power dissipation.
There thus remains a need for a switched-capacitor pipeline ADC stage, which provides a reduction in inter-symbol interference, without significantly increasing power dissipation.